1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, relates to a semiconductor integrated circuit for dropping an external power source voltage to thereby obtain an internal power source voltage
2. Description of the Relevant Art
In general, it is preferable that miniaturization of semiconductor elements continue so that the integration level of semiconductor integrated circuits can be enhanced. However, the further miniaturization of semiconductor elements leads to such disadvantages as a lowering of the pressure resistance thereof and the possibility that the element will be adversely influenced by hot electrons.
As an effective countermeasure against these inconveniences, is the lowering of the power source voltage to be supplied to the semiconductor element so as to minimize the electric field strength of the respective portions of the element. For example, the destruction by aging of an oxidated film can be prevented by lowering the electric field strength of the oxidated film. Further, by lowering the channel electric field strength, the generation of hot electrons can be suppressed to thereby reduce the amount of hot electrons injected into the oxidated film, i.e., the hot electron instability (concretely, the variation of threshold value V.sub.th and a poor conductance) can be prevented.
Many of the problems arising in miniaturized elements can be solved if the power source voltage is thus lowered, but it is not preferable for the preparation of an exclusive-use external power source because the system becomes complex and dedicated power source wires are required. Therefore, the method of dropping the external power source voltage inside a semiconductor integrated circuit to thus form a low voltage internal power source is generally adopted. FIG. 1 and FIG. 2 show the structure of a conventional semiconductor integrated circuit for dropping the external power source voltage inside the semiconductor integrated circuit in order to produce a low voltage internal power source. In FIG. 1, VccPAD is a power source terminal installed at a semiconductor chip, to which the external power source is to be applied, "A" is a voltage drop circuit, and C11 through C1n represent a plurality ("n" units) of semiconductor circuits The power source terminal VccPAD is installed, usually as one body, on the semiconductor chip 2, and the semiconductor circuits C11 through C1n are two-dimensionally arranged in the plane of the semiconductor chip 2. The voltage drop circuit "A" forms an internal power source voltage Vint, which drops the external power source voltage applied to the power source terminal VccPAD, to a given voltage. This external voltage is a common power source voltage which is also applied to the other semiconductor integrated circuits and is, for example, +5 V. The voltage is dropped to a given level by utilizing, for example, the channel resistance of a MOS transistor.
The given voltage referred to herein means the voltage necessary for the actuation of a miniaturized semiconductor element (for example, a MOS transistor) forming a structure of a plurality of internal semiconductor circuits C11 through C1n, and moreover, which effectively avoids a pressure resistance and hot electrons.
FIG. 3 shows an example of semiconductor circuits C11 through C1n given in FIG. 1, wherein the semiconductor integrated circuit is a dynamic RAM. In this FIGURE, C.sub.11 is a mode control circuit, C.sub.12 a refresh address counter, C.sub.13 an address buffer, C.sub.14 a pre-decoder, C.sub.15 a basic bias generating circuit, C.sub.16 a sense amplifier driver, C.sub.17 a first clock generating circuit, C.sub.18 a gate circuit, C.sub.19 a second clock generating circuit, C.sub.20 a write clock generating circuit, C.sub.21 a column decoder, C.sub.22 a low decoder, C.sub.23 a date input buffer and C.sub.24 a data output buffer, and the internal power source voltage, which has been dropped by the voltage drop circuit "A," can be supplied to each of these semiconductor circuits C11 through C24. FIG. 4A is a circuit diagram showing the structure example of the address buffer of FIG. 3, whereas FIG. 4B is a circuit diagram showing the structure example of the pre-decoder of FIG. 3.
In this type of conventional semiconductor integrated circuit, however, because a plurality of internal semiconductor integrated circuits (C11 through C1n in FIG. 1, and C.sub.11 through C.sub.1n in FIG. 3) use a single internal power source voltage Vint in common there is a danger that the potential of Vint will instantaneously drop, and thus the other semiconductor circuits may malfunction because of this; for example, when a semiconductor circuit consuming a very large current is actuated outside of these internal semiconductor circuits (C11 through C1n in FIG. 1 and C.sub.11 through C.sub.1n in FIG. 3).
Therefore, a technique is employed such as the installation of a circuit to detect the voltage drop of the internal power source voltage Vint, and supplying a comparatively large current when the voltage drop has been detected, thus suppress the fluctuations of internal power source voltage. In this method, however, a delay in the response, to a certain degree, was unavoidable until the current was supplied after the actual voltage drop, and as a result, the conventional circuit could not properly or effectively suppress the instantaneous voltage drop of the internal power source voltage Vint.